- Name:
- srlatch
- Syntax:
-
SRLATCH config1, config2
Config1 - is a variable/constant which specifies the latch configuration
Bit 7 = 1 SR Latch is active = 0 SR Latch is not used Bit 6-4 SR Clock Divider Bits - sets latch clock frequency Divider 16MHz 8MHz 4MHz = 000 1/4 0.25us 0.5us 1us = 001 1/8 0.5 1 2 = 010 1/16 1 2 4 = 011 1/32 2 4 8 = 100 1/64 4 8 16 = 101 1/128 8 16 32 = 110 1/256 16 32 64 = 111 1/512 32 64 128 Bit 3 = 1 Q is present on pin SRQ (when an output) = 0 Pin SRQ is not used by the SR Latch module Bit 2 = 1 NOT Q is present on pin SRNQ (when an output) = 0 Pin SRNQ is not used by the SR Latch module Bit 1 = 0 Not used, leave as 0 Bit 0 = 0 Not used, leave as 0 Note that not all parts have both SRQ and SRNQ pins. Some parts have just SRQ and some have just SRNQ. See the pin out diagrams for the PICAXE chip in use. Note also that as SRNQ on the 28X2/40X2 parts is the 'serial out' programming pin debug and sertxd commands will not function when SRNQ is set active (via bit 2).
Config2 - is a variable/constant which specifies the set/reset configuration. When the bit is low the feature has no effect on the SR latch.
For 20X2 part:
Bit 7 = 1 HINT1 sets latch (see hintsetup) Bit 6 = 1 Latch set pin is pulsed by clock (see above) Bit 5 = 1 C2 comparator sets latch (see compsetup) Bit 4 = 1 C1 comparator sets latch (see compsetup) Bit 3 = 1 HINT1 resets latch (see hintsetup) Bit 2 = 1 Latch reset pin is pulsed by clock (see above) Bit 1 = 1 C2 comparator resets latch (see compsetup) Bit 0 = 1 C1 comparator resets latch (see compsetup) For 28X2/40X2 parts:
Bit 7 = 1 SRI pin high sets latch Bit 6 = 1 Latch set pin is pulsed by clock (see above) Bit 5 = 1 C2 comparator sets latch (see compsetup) Bit 4 = 1 C1 comparator sets latch (see compsetup) Bit 3 = 1 SRI pin high resets latc Bit 2 = 1 Latch reset pin is pulsed by clock (see above) Bit 1 = 1 C2 comparator resets latch (see compsetup) Bit 0 = 1 C1 comparator resets latch (see compsetup) Note that on 28X2/40X2 parts the SRI pin can act as either a set or reset pin by setting bit 3 or bit 7. Do not set both bits at the same time!
For M2 parts:
Bit 7 = 1 SRI pin high sets latch Bit 6 = 1 Latch set pin is pulsed by clock (see above) Bit 5 = 0 Not used, leave as 0 Bit 4 = 0 Not used, leave as 0 Bit 3 = 1 SRI pin high resets latch Bit 2 = 1 Latch reset pin is pulsed by clock (see above) Bit 1 = 0 Not used, leave as 0 Bit 0 = 0 Not used, leave as 0 Note that on M2 parts the SRI pin can act as either a set or reset pin by setting bit 3 or bit 7. Do not set both bits at the same time!
- Description:
-
Setup the internal hardware SR latch.
The latch can be set by the SRSET command, or one of the peripherals listed above. Similarly the latch can be reset by the SRRESET command or one of the peripherals. If both SET and RESET signals are present the latch goes to the RESET state. Some PICAXE microcontrollers have an internal hardware SR latch. This latch can be used independently of the PICAXE program, so that, for instance, an output can be INSTANTLY controlled directly via the latch.
The SR latch also contains an internal clock source. This means the SR latch can be optionally configured to act like a '555 timer'.
The output (Q) of the latch can be made available on pin SRQ (if present). The inverse of the output (NOT Q) can be made available on pin SRNQ (if present). The srlatch command does not automatically configure these pins as outputs, this must be carried out by the user program before use.
- Applies To:
- 08M2, 14M2, 18M2, 20M2, 20X2
- See Also:
- Related Create:
Setting and resetting the latch output
This program configures the SR latch for use and then repeatedly sets and resets the latch.
- Code Example:
-
#picaxe 20x2 init: low B.1 ; Set SRQ output low high C.4 ; Set SRNQ output high srlatch %10001100, %00000000 ; Enable latch, use SRQ and SRNQ as outputs main: srset ; set the latch (SRQ high, SRNQ low) pause 5000 srreset ; reset the latch (SRQ low, SRNQ high) pause 5000 goto main ; loop back to start
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